This invention relates to a limiter circuit for the maximum current passed from a power transistor to a load connected between one output terminal of the transistor and a first terminal of a voltage supply.
In particular, the invention relates to a limiter circuit for the maximum current passed from a power transistor to a load connected between a first output terminal of the transistor and a first voltage supply pole, of the type which includes (as shown in FIG. 1): a driver stage for said transistor, having an input terminal adapted to receive a control signal and an output terminal connected to the control terminal of said transistor; an error amplifier incorporating a current generator and having two input terminals and an output terminal connected to said driver stage; and a circuit for detecting the current being flowed through said load, having a first terminal connected to a second output terminal of said transistor and a second terminal connected to a second supply pole.
There are many ways of limiting the maximum current through a load connected to an output terminal of a power transistor. The most widely used method provides a feedback network comprising an error amplifier, one input whereof is connected to a reference voltage and the other input to a circuit means of detecting the current flowing through the load, while its output is connected to the control terminal of the transistor. That error amplifier basically performs a comparison between the reference voltage with that applied to the other of its inputs, which voltage increases with the current through the load. When these two voltages tend to become equal to each other, the error amplifier output will limit the current at the transistor control terminal, and accordingly, limit the current at the output terminal connected to the load.
A major problem to be faced with such negative feedback arrangements is one of stability, especially where the load connected to the transistor is an inductive one. In fact, a load of this type introduces undesired poles into the transfer function, so that it becomes difficult to compensate the negatively fed-back transistor for frequency because the transistor is liable to begin to oscillating as soon as the error amplifier cuts in.
The circuit disclosed in European Patent No. 0151764-B, which is hereby incorporated by reference and which corresponds to U.S. Pat. No. 4,574,221, is exemplary of an effective compensation, that is, of a negatively fed-back power transistor which stays stable even as the error amplifier in the feedback network cuts in to limit the load current. In that circuit, the transfer function of the transistor is altered by connecting, in the feedback network, a circuit means which comprises a diode-configured transistor and a transistor. The latter has its base connected to a circuit node whose voltage relative to a reference (ground) potential varies according to the load current, and its emitter is impressed with a resistance connected to one leg of the input stage of the error amplifier, the other input of the latter being held at a constant potential. The diode has one terminal connected to a resistor which "senses" the current flowing through the load, and another terminal connected to said transistor base resistor, and hence, to one of the error amplifier inputs. The load current variations reflect as voltage variations across the diode, which variations are known to be of a logarithmic type, that is quite marginal. Thus, such modest voltage variations are transferred to said error amplifier input not held at a constant potential.
The introduction of said circuit means into the feedback network of the power transistor creates a local reaction whose overall effect is of decreasing the voltage gain of the open-loop system, thereby conferring stability on it. However, the action of the error amplifier in limiting the load current still tends to be jerky, causing the increase in load current to stop suddenly before the load current has settled at a constant value.
The underlying technical problem of this invention is to provide a limiter circuit for the maximum current passed from a power transistor to a load connected to an output terminal thereof, wherein the reduction of any load current rise can occur gradually, without any sharp limiting effect and while maintaining a stable condition for the circuit.
This problem is solved, in accordance with innovative teachings of the present application, by using a limiter circuit for the maximum current passed from a power transistor (T'p) to a load (ZL) connected to an output terminal of the transistor, being of a type which comprises an error amplifier (1'), a driver circuit (P') for said transistor (T'p), and a means of detecting the current (IL) flowing through said load (ZL) provided with at least first and second terminals, comprises a circuit block (2) having an input terminal connected to the control terminal of (T'p) and an output terminal connected to the current generator internal of the amplifier (1'), one input (B') of said amplifier (1') being connected to said first terminal of (Rs) and the other input (A') connected to said second terminal of (Rs). The introduction of said circuit block lowers the open-loop system gain making it stable and producing a smooth reduction of any rise in the load current (IL).